Computer Architecture and Organisation The Development

Question: Discuss about a Research Proposal for Computer Architecture and Organisation in The Development ? Answer: Introduction The accumulation recollection of a central processing unit represents the memory which can be readily accessed if required. The cache memory provides faster relay functions compared to the RAM. The cache memory is highly integrated into the CPU and is called upon when needed. The cache memory has many bus connections plugged to perform smoothly on the system. The question provides us with the main memory consisting of 16 bit memory address. The capacity for the memory that the 16 bit memory address provides = 216 = 65536 bytes of memory. Initially the memory is 65536 bytes and with the size of cache catch up variations like 64,128,256 bytes. In the next step we go through the words installed in every block of the cache memory and are varied like 1, 2 and 4 (Stallings, 2000). So we know that per block of cache memory may tag in 1 word, 2 words, or 4 words. Then the cache and the words contained in it vary like 16, 32 and 256 respectively per block. In the third step we are provided with the conjunctures to divide main memory and arrange it accordingly to direct mapping, we are provided with full associative of the memory (i.e. 2, 4 and 8) and then a second set of associates which gives a total of five. The division of the memory address takes place with the help of N set of associates. Overview of the simulation model The simulation model which we are concerned about deals with the cache memory that can work on different memory address, can work independent of different word per block and also different cache size. The concerned simulation model then deals with 17 cases of different memory address and other parameters of different cache organizations. The main memory address takes in variations like (1, 2, 4, 8 and 16) setting up associative mapping which calls out for 16 bit memory byte address to as 65536 bytes, 32768 bytes, 16384 bytes, 8192 bytes, 4096 bytes respectively for each block. In the second case the words per block of the cache in variations according to 1/2/4 words per block. Each word would consist of 4 bytes. And the result will be like 4 bytes, 8 bytes, 16 bytes for 1 word, 2 words and 4 words respectively for per cache block. The thirds case deals with the size of the cache which is varied from 64 byte, 128 byte, 256 byte which means that the cache lines can be terminated from this (Blanchet and Dupouy, 2013). 64 bytes of cache resulting in 26 bytes which represents 6 cache lines, 128 bytes of cache resulting in 27 bytes which represents 7 cache lines as well as it is for 256 bytes cache size which sums up to 28 bytes which portrays 8 cache lines. Simulation code: #include #include #include #define stream 1 //0 to print screen, 1 to write cache.txt #define main_memory 65536 //65536, 32768, 16384, 8192, 4096 addressable memory (1, 2, 4, //8, 16 way set associativity respectively) #define cache_line 64 //M can be 64, 128, 256 bytes that means // 26,27,28 bytes which says 6,7,8 cache lines respectively #define cache_block_size 1 //N can be 1/2/4 word in each cache line int cache_tag[cache_line]; //cache tag //if(cache_tag(i)==0, its=MISS) int total_memory_access=0; //amount of memory access or //address request from CPU int total_hit=0; //amount of cache hit //print the hit ratio void print_hit_ratio(void) { float ratio; if (total_hit==0) ratio=0; else ratio=(float)total_hit/(float)total_memory_access; } //reading input file line by line void input() { int ifp=0, address_requested; while(fscanf(ifp,"hdn",address_requested !-EOP) { int done=0; for(i=0;icache_line;i++) { if(address_requested=cache_tag[1] (address_requested=cache_tag[1]cache_bloc_size) { total_hit++; done=1; break; } } if (done==0) { lastwrote=(++lastwrote)%cache_line; cache_tag(lastwrote)=address_requested; } total_memory_access++; } } //print the content of cache table write_cache_table() { int i; int j; FILE *ofp; /output file pointer if(stream) ofp=fopen(cache.out,"w"); else ofp=stdout; //print table header fprintf(ofp,%d),"Lines"); for(i=0;icache_block_size;i++) { fprintf(ofp,"%6d",i); } fprintf(ofp "n" ); for(i=1;icache_block_size;i++) { fprintf(ofp,"---------"); } fprintf(of,"n"); //loop with cache line for(i=0;icache_line;i++) { fprintf(ofp,"%6d",i); } for(j=0;jcache_block_size;j++) { //no content in cache if(cache_tag[i]==0); { fprint(ofp,"%6d",0); else frintf(ofp, "%6f",cache_tag[i]=j); } fprintf(ofp,"n"); } fclose(ofp); } int usage(void) { printf("Please pass a field n"); printf("Usage: caches in n"); } int main(int argo, char *argv[]) { FILE *ifp; //input file int address_requested=0; //address sequential clrscr(); if (argo!= 2) { exit(usage()); } //read input file from command line ifp=fopen(argv[i], "r"); if(ifp==NULL) { printf("ERROR File does not exist :n ".argv[i]); exit(usage()); } print_hit_ratio(); input(); write_cache_table(); fclose(ifp); getch(); } Conclusion The conclusion gained from the topic is that the cache memory can be varied according to the set of associative created; the size of the cache can be varied according to the number of words. For a mock result we represent a cache of 64 bytes with 1/2/4 word block can have 16/8/4 words respectively in cache size. In the second case when the memory of the cache has capacity of 128 bytes with 1/2/4 word block then it can have 32/16/8 words respectively in memory. The last phenomena if the concerned cache memory has got 256 bytes with 1/2/4 words per block then it should consist of 64/32/16 words. References Baron, R. and Higbie, L. (1992).Computer architecture. Reading, Mass.: Addison-Wesley Pub. Co. Blanchet, G. and Dupouy, B. (2013).Computer architecture. London: Iste. Brandon, J. (1981).The Development of a microprocessor based modal analysis system. University of Manchester Institute of Science and Technology. Dorfman, L. (1991).80386 protected mode programming in C. Blue Ridge Summit, PA: Windcrest. Fitz, R. and Crockett, L. (1986).Universal assembly language. Blue Ridge Summit, PA: Tab Books. Harris, D. and Harris, S. (2007).Digital design and computer architecture. Amsterdam: Morgan Kaufmann Publishers. Hennessy, J., Patterson, D. and Arpaci-Dusseau, A. (2007).Computer architecture. Amsterdam: Elsevier/Morgan Kaufmann Publishers. Holland, R. (1989).Microprocessors and their operating systems. Oxford: Pergamon. Hwang, K. and Briggs, F. (1984).Computer architecture and parallel processing. New York: McGraw-Hill. Hyder, K. and Perrin, B. (2005).Embedded systems design using the Rabbit 3000 microprocessor. Amsterdam: Newnes. Katzen, S. (1994).C for the microprocessor engineer. New York: Prentice Hall. Kernighan, B. and Ritchie, D. (1988).The C programming language. Englewood Cliffs, N.J.: Prentice Hall. Lindecrantz, K. (1983).Processing of the fetal ECG. Goteborg, Sweden: Chalmers University of Technology. Lipovski, G. (1990).16- and 32-bit microcomputer interfacing. Englewood Cliffs, N.J.: Prentice-Hall. Payne, R. (1987).The design of a tightly coupled multiple microprocessor system. Cardiff: University College. Robinett, J. (1976).Extension of a 16-bit microprocessor system. Said, S. (1985).Design and development of a high-performance microprocessor system for the implementation of digital signal processing algorithms. University of Kent at Canterbury. Shriver, B. and Smith, B. (1998).The anatomy of a high-performance microprocessor. Los Alamitos, Calif.: IEEE Computer Society. Spruth, W. (1989).The Design of a Microprocessor. Berlin, Heidelberg: Springer Berlin Heidelberg. Stallings, W. (2000).Computer organization and architecture. Upper Saddle River, N.J.: Prentice Hall. Still, P., Burtwell, M. and Young, J. (1983).Evaluation of a microprocessor system for bump-integrators. Crowthorne, Berkshire: Transport and Road Research Laboratory. Stroustrup, B. (1997).The C++ programming language. Reading, Mass.: Addison-Wesley. Traister, R. (1994).Conquering C++ pointers. Boston: Academic Press Professional. Weiskamp, K. (1994).The Borland C++ 4.0 primer. Boston: AP Professional. Willen, D. and Krantz, J. (1983).8088 assembler language programming. Indianapolis, Ind.: H.W. Sams. Wilson, A. (1980).A microprocessor system for the analysis of cardio-respiratory data. University of Sheffield. Wilson, G. (2002).Embedded systems and computer architecture. Oxford: Newnes. Yeung, B. (1984).8086/8088 assembly language programming. Chichester: J. Wiley.